UNIT I THE MICROPROCESSOR. Microprocessor architecture- Addressing modes- Instruction set-Programming the Objective: To have an in. CS / CS42 / EC / CS / Micro Processors and Micro Controllers Complete Notes CSE,IT 4th Semester regulation EC Microprocessor and Microcontroller Lecture Notes All 5 Units – Free notes for Anna university 4TH sem Subject CS MICROPROCESSORS AND.
| Author: | Mazucage Fenrimuro |
| Country: | Bosnia & Herzegovina |
| Language: | English (Spanish) |
| Genre: | Music |
| Published (Last): | 14 August 2007 |
| Pages: | 66 |
| PDF File Size: | 11.23 Mb |
| ePub File Size: | 8.95 Mb |
| ISBN: | 288-5-78358-955-8 |
| Downloads: | 80943 |
| Price: | Free* [*Free Regsitration Required] |
| Uploader: | Tojak |
The RSC serial bus is usually terminated using either a 9-pin connector or microconttoller pin connector. What is the difference between register and memory? List the important features of It translates assembly language program to a machine language program. ZF is set, zero for non zero results. The decoded outputs repeat the pattern ,, and Microprocessors and Microcontrollers impractical or impossible.
Microprocessor based system has limitation on size of data, less execution speed, limited address space, does not support floating point operations. Cd2252 process of signing a label or macro name to the string operation is defining a macro.
‘+relatedpoststitle+’
If more than one-channel requests services simultaneously the transfer is called as burst transfer. Stack segment register points to the current stack. OF is set if there is a arithmetic overflow.
If a key code is generated immediately after sensing a key actuation, then the processor will generate microcontrollet same key code a number of times. Speed operation Can solve complex problems Can be acted as microprocesosr processor 3. When terminal TC output pin is high one level outputit indicates that the terminal count register count is zero.
TCON has control bits and flags for the timers in the upper nibble and control bits and flags for the external interrupts in the lower nibble.
Explain microclntroller output modes of The RSC is a serial bus consisting of a maximum of 25 signals. It is often referred to as universal asynchronous receiver transmitter or UART. What is the hardware interrupts of ? The string instructions assume S1 to point to first byte or work of the source operand and D!
Condition code or status flag register. Simple input and output. Usually a microprocessor will be the CPU of microprocezsor system and it is called the brain of the computer.
How to enable these interrupts? What is In-service register ISR? Polling is employed when multiple devices interrupt the processor through one interrupt pin of the processor.
The status word can read by the CPU to check the readiness of the transmitter or microprocsesor and to check the character synchronization in synchronous reception can read. The segment register contains bit segment base addresses, related to different segments. What is meant by multiplexing? In asynchronous transmission, sometimes referred to as start-stop transmission, start and stop bit intervals are transmitted with each byte of information for the purpose of synchronization.
Usually the first 9-signals are sufficient for most of the serial data transmission. Hence the processor has to wait for the key bounces to settle before reading the key code. All these interrupts are vectored interrupts. The data are often transferred through telephone wire or over the airwaves via form of radio carriers. Then the device can start and stop according to the program.
Microprocessors and Micro controllers Two Marks with answers | Devasena A. –
What is assembler directive? Why interrupt flag IF is automatically cleared? Interrupt is a process of stopping the normal program execution for some time by a special instruction in the program.
How many words of RAM available in the display controller of ?
They are used as segment registers, pointers, index registers or as offset storage registers for particular addressing modes.
